Complementary metal-oxide semiconductor (CMOS) processing is commonly used in the fabrication of digital integrated circuits (ICs) which operate at bit rates typically on the order of 100 Mb/s. At these speeds there is less concern about the effect of parasitic capacitance and resistance, thus enabling the use of standard twin-tub CMOS transistor designs with polysilicon gates.
In many analog applications at significantly higher speeds (e.g., above the 900 MHz speed encountered in many wireless applications) reduction of parasitics is particularly important. The prior art has attempted to address this problem by altering the fundamental CMOS transistor design, for example, by substituting a metal (e.g., Mo) gate for the polysilicon gate and by using very wide gates (e.g., gate widths of 100 .mu.m). I. Yoshida et al., Electronics and Communications in Japan, Part 2, No. 77, No. 4, pp. 10-19 (1994), have taken this approach in their design of RF power amplifiers. However, significantly changing a standard CMOS process can be a very expensive proposition, entailing re-qualification of the CMOS manufacturing line with attendant high cost and likely lower yields. In addition, the device redesign for high power applications is often not optimum for low noise applications.
Thus, a need remains in the art for a LNA which can be implemented using conventional CMOS fabrication processes and transistor designs.